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rclamp0524pq final datasheet rev 2.0 revision date june 22, 2015 www.semtech.com 1 of 10 semtech protection products features ? transient protection to s iec 61000-4-2 (esd) 25kv (air), 15kv (contact) s iec 61000-4-4 (eft) 4kv (5/50ns) s iec 61000-4-5 (lightning) 5a (8/20s) s iso-10605 (esd) 20kv (air), 12kv (contact) ? quali ed to aec-q100, grade 1 ? protects four high-speed data lines ? working voltage: 5v ? low capacitance: 0.8 pf maximum (i/o to gnd) ? dynamic resistance: 0.43 ohms (typ) ? solid-state silicon-avalanche technology mechanical characteristics ? slp2510p8 package ? pb-free, halogen free, rohs/weee compliant ? nominal dimensions: 2.5 x 1.0 x 0.58 mm ? lead finish: nipdau ? molding compound flammability rating: ul 94v-0 ? marking : marking code + date code ? packaging : tape and reel applications ? automotive applications ? industrial equipment ? hdmi ? digital visual interface ? mddi ports ? pci express rclamp0524pq low capacitance railclamp? 4-line surge and esd protection description railclamp? tvs arrays are ultra low capacitance esd protection devices designed to protect high speed data interfaces. this series has been speci cally designed to protect sensitive components which are connected to high-speed data and transmission lines from overvoltage caused by esd (electrostatic discharge), cde (cable discharge events), and eft (electrical fast transients). rclamp0524pq has a typical capacitance of only 0.3 pf between i/o pins. this allows it to be used on circuits operating in excess of 3ghz with no signi cant signal attenuation. esd characteristics are highlighted by high esd withstand voltage (+/-15kv per iec 61000-4-2) and low dynamic resistance (0.43 ohms typical). each device will protect four lines operating at 5 volts rclamp0524pq is in a 10-pin slp2510p8 package and is quali ed to aec-q100, grade 1 (-40 to +125 o c) for automotive applications. it measures 2.5 x 1.0 mm with a nominal height of only 0.58 mm. the leads are nished with lead-free nipdau. the ow- through package design simpli es pcb layout. $,"% !"#$ %.#.$ !,"$ #,$$ a *.0 & $ + % %$+@6&6 nominal dimension functional schematic device schematic nominal dimensions in mm
rclamp0524pq final datasheet rev 2.0 revision date june 22, 2015 www.semtech.com 2 of 10 semtech absolute maximum rating rating symbol value units peak pulse power (tp = 8/20s) p pk 75 w peak pulse current (tp = 8/20s) i pp 5 a esd per iec 61000-4-2 (contact) (1) esd per iec 61000-4-2 (air) (1) v esd 1525 kv esd per iso-10605 (contact) (2) esd per iso-10605 (air) (2) v esd 12 20 kv operating temperature t j -40 to +125 o c storage temperature t stg -55 to +150 o c electrical characteristics (t=25 o c unless otherwise sp eci ed) parameter symbol conditions min. typ. max. units reverse stand-o voltage v rwm -40 o c to 125 o c any i/o pin to gnd 5 v reverse breakdown voltage v br i t = 10ma, any i/o pin to gnd -40 o c to 125 o c 6.5 9 11 v reverse leakage current i r v rwm = 5v t = 25 o c 0.1 a t = 125 o c 0.25 a clamping voltage (3) v c i pp = 1a, tp = 8/20s, any i/o pin to gnd 12 v clamping voltage (3) v c i pp = 5a, tp = 8/20s, any i/o pin to gnd 15 v esd clamping voltage (4) v c i pp = 4a, tp = 0.2/100ns (tlp) any i/o pin to gnd 12 v esd clamping voltage (4) v c i pp = 16a, tp = 0.2/100ns (tlp) any i/o pin to gnd 17 v dynamic resistance (4), (5) r dyn tp = 0.2/100ns (tlp) any i/o pin to gnd 0.43 ohms junction capacitance c j v r = 0v, f = 1mhz any i/o pin to gnd t = 25 o c 0.4 0.8 pf t=125 o c 1.2 1.5 v r = 0v, f = 1mhz between i/o pins t = 25 o c 0.3 0.4 t = 125 o c 0.5 0.7 notes: (1): esd gun return path to ground reference plane (grp) (2): esd gun return path to horizontal coupling plane (hcp); test conditions: 330pf, 330 ?. (3): measured using an 8/20us constant current source. (4): transmission line pulse test (tlp) settings: tp = 100ns, tr = 0.2ns, i tlp and v tlp averaging window: t 1 = 70ns to t 2 = 90ns. (5): dynamic resistance calculated from i tlp = 4a to i tlp = 16a
rclamp0524pq final datasheet rev 2.0 revision date june 22, 2015 www.semtech.com 3 of 10 semtech typical characteristics non-repetitive peak pulse power vs. pulse time power derating curve 8/20us surge clamping characteristic esd clamping (+8kv contact per iec 61000-4-2) 0 5 10 15 20 0 1 2 3 4 5 6 7 8 9 peak clamping voltage - v c (v) peak pulse current - i pp (a) rc0524pq_ar_8_20 lg t a = 25 o c waveform 8x20us any pin to gnd 0 20 40 60 80 100 120 140 160 -20 0 20 40 60 80 100 clamping voltage - v c (v) time (ns) t a = 25 o c. waveform iec61000-4-2 +8kv. measured with and corrected for 50, 40db attenuator. 50 scope input impedance, 2ghz bw. esd gun return connected to ground reference plane . rc0524pq_ar_p8_esd 0 5 10 15 20 25 30 0 5 10 15 20 25 dut current (a) dut voltage (v) rc0524pq_ar_tlp_pos t a = 25 o c any pin l-g t p = 100ns, t r = 0.2ns t meas = 70-90ns rdyn = 0.43? (4a-16a best fit) -250 -200 -150 -100 -50 0 -20 0 20 40 60 80 100 clamping voltage - v c (v) time (ns) t a = 25 o c. waveform iec61000-4-2 -8kv. measured with and corrected for 50, 40db attenuator. 50 scope input impedance, 2ghz bw. esd gun return connected to esd ground plane . rc0524pq_ar_n8_esd 0.01 0.1 1 10 0.1 1 10 100 1000 peak pulse power - p pp (kw) pulse duration - tp (s) dr040412-75 t a = 25 o c 0 20 40 60 80 100 120 0 25 50 75 100 125 150 % of rated power or i pp ambient temperature - t a ( o c) dr040512:25:125:150 tlp iv curve (positive pulse) esd clamping (-8kv contact per iec 61000-4-2)
rclamp0524pq final datasheet rev 2.0 revision date june 22, 2015 www.semtech.com 4 of 10 semtech typical characteristics (continued) esd clamping (+12kv contact per iso-10605 330pf, 330 ? ) esd clamping (-12kv contact per iso-10605 330pf, 330 ? ) 0 50 100 150 200 -20 0 20 40 60 80 100 clamping voltage - v c (v) time (ns) t a = 25 o c. waveform iso10605 +12kv. r = 330 ?; c = 330pf measured with and corrected for 50, 40db attenuator. 50 scope input impedance, 2ghz bw. esd gun return connected to horizontal coupling pla ne . rc0524pq_ar_iso330330_p12_esd -300 -250 -200 -150 -100 -50 0 -20 0 20 40 60 80 100 clamping voltage - v c (v) time (ns) t a = 25 o c. waveform iso10605 -12kv. r = 330?; c = 330pf measured with and corrected for 50, 40db attenuator. 50 scope input impedance, 2ghz bw. esd gun return connected to horizontal coupling pla ne . rc0524pq_ar_iso330330_n12_esd capacitance vs. reverse voltage insertion loss - s21 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 1 2 3 4 5 6 capacitance - c j (pf) reverse voltage - v r (v) t a = 25 o c. f = 1 mhz. any pin l-g rc0524pq_ar_capvv -10 -8 -6 -4 -2 0 0 2 4 6 8 10 insertion loss - il (db) frequency (ghz) rc0524pq_ar_il 0.0 0.5 1.0 1.5 -50 0 50 100 150 capacitance - c j (pf) temperature ( o c) l-g l-l vr = 0v f = 1mhz rc0524pq_ar_cjvt 9.0 9.5 10.0 10.5 11.0 -50 0 50 100 150 breakdown voltage - v br (v) temperature ( o c) ibr = 10ma l-g ibr = 10ma l-l rc0524pq_ar_vbrvt capacitance vs. temperature breakdown voltage (vbr) vs. temperature
rclamp0524pq final datasheet rev 2.0 revision date june 22, 2015 www.semtech.com 5 of 10 semtech applications information assembly guidelines the small size of this device means that some care must be taken during the mounting process to insure reliable solder join t. the gure at the right details semtechs rec- ommended mounting pattern. recommended assembly guidelines are shown in table 2. note that these are only recommendations and should serve only as a starting point for design since there are many factors that a ect the assembly process. exact manufacturing parameters will require some experimentation to get the desired solder application. semtechs recommended mounting pattern is based on the following design guidelines: land pattern the recommended land pattern follows ipc standards and is designed for maximum solder coverage. detailed dimensions are shown elsewhere in this document. solder stencil stencil design is one of the key factors which will determine the volume of solder paste which is deposited onto the land pad. the area ratio of the stencil aperture will determine how well the stencil will print. the area ratio takes into account the aperture shape, aperture size, and stencil thickness. the area ratio of a rectangular aperture is given as: area ratio = (l * w )/ (2 * (l + w) * t) where: l = aperture length w = aperture width t = stencil thickness semtech recommends a stencil thickness of 0.100mm - 0.125mm for this device. the stencil should be laser cut with electro-polished nish. the stencil should have a positive taper of approximately 5 degrees. electro polishing and tapering the walls results in reduced surface friction and better paste release. due to the small aperture size, a solder paste with type 4 or smaller particles is recommended. assuming a 125um thick stencil, the aperture dimensions shown will yield an area ratio of 0.72 for the small pads and 1.25 for the large. recommended stencil design !"#$ %.5.$ $,5c" $,!$ (1(* #,"" $,"$ $,:$ $,!$ $,!" )1(* table 2 - recommended assembly guidelines assembly parameter recommendation solder stencil design laser cut, electro-polished aperture shape rectangular solder stencil thickness 0.100mm (0.004) - 0.125mm (0.005) solder paste type type 4 size sphere or smaller solder re ow pro le per jedec j-std-020 pcb solder pad design non-solder mask de ned pcb pad finish osp or niau design recommendations for hdmi protection adding external esd protection to hdmi ports can be challenging. first, esd protection devices have an inherent junction capacitance and adding even a small amount of capacitance will cause the impedance of the di erential pair to drop. second, large packages and land pattern requirements cause discontinuities that adversely a ect signal integrity. the rclamp0524pq is speci cally designed for protection of high-speed interfaces such as hdmi. it presents <0.4pf capacitance between the pairs while being rated to handle >8kv esd contact discharges (>15kv air discharge) as outlined in iec 61000-4-2. each device is in a leadless slp package that is less than 1.1mm wide. it is designed such that the traces ow straight through the device. the narrow package and ow-through design reduces discontinuities and minimizes impact on signal integrity. this becomes more critical as signal speeds increase.
rclamp0524pq final datasheet rev 2.0 revision date june 22, 2015 www.semtech.com 6 of 10 semtech applications information pin con guration figure 1 is an example of how to route the high speed di erential traces through the rclamp0524pq. the solid line represents the pcb trace. the pcb traces are used to connect the pin pairs for each line (pin 1 to pin 10, pin 2 to pin 9, pin 4 to pin 7, pin 5 to pin 6). for example, line 1 enters at pin 1 and exits at pin 10 and the pcb trace connects pin 1 and 10 together. this is true for lines connected at pins 2, 4, and 5 also. ground is connected at pins 3 and 8. one large ground pad should be used in lieu of two separate pads. figure 1. flow through layout using rclamp0524pq tdr measurements for hdmi the combination of low capacitance, small package, and ow-through design means it is possible to use these devices to meet the hdmi impedance requirements of 100 ohms 15% without any pcb board modi cation. figure 3 shows a typical impedance test result for a tdr risetime of 200ps using a semtech evaluation board with 100 ohm traces throughout. measurements were taken using a tdr method as outlined in the hdmi compliance test speci cation (cts). in each case, the device meets the hdmi cts requirement of 100 ohm 15% with 1 , 2
& $ * + % # / 0 4 & && &$ %$+@606 & a a & a a plenty of margin (98.3 at 1.79 ns). figure 2 - tdr measurement with 200ps risetime using semtech evaluation board figure 3 shows a typical hdmi 1.4 eye pattern at 1080p resolution. as shown there are no violations of the eye pattern with rclamp0524pq in the circuit. the rclamp0524pq may also be used to protect the remaining lines (i2c, cec, and hot plug). figure 3 - hdmi 1.4 eye pattern with rclamp0524pq
rclamp0524pq final datasheet rev 2.0 revision date june 22, 2015 www.semtech.com 7 of 10 semtech layout guidelines for optimum esd protection good circuit board layout is critical not only for signal integrity, but also for e ective suppression of esd induced transients. for optimum esd protection, the following guidelines are recommended: ? place the device as close to the connector as possible. this practice restricts esd coupling into adjacent traces and reduces parasitic inductance. ? the esd transient return path to ground should be kept as short as possible. whenever possible, use multiple micro vias connected directly from the device ground pad to the ground plane. ? avoid running critical signals near board edges. note: measurements were taken on slp hdmi eval rev c board applications information figure 4. hdmi 1.4 application using rclamp0524pq %$+@646 a a , $6 , $e , &6 , &e , 6 , e , df6 , dfe a d 1

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rclamp0524pq final datasheet rev 2.0 revision date june 22, 2015 www.semtech.com 8 of 10 semtech outline drawing - slp2510p8 land pattern - slp2510p8 $,"$ $,"%$ $,5" 7 7 7 7& 7 7 7= $,$$ $,$9 $,$" # $,#" $,!$ $,!" $,9" $,:$ $,:" # !,:$ !,"$ !,5$ $,>$ #,$$ #,#$ $,"$ $,9$ $,9% $,:9 % $,$% $,#$ &; # # & ? 7@a # ! !b$,$c" c ) 4! b 4! !b# 7 7 $,#!" b &' #& ; 77 7&4; ; !"#$ %.!.$ ?$,#9a ! !"#$ %.9.$ &' #,& ; 77 7&?; ;a, !,&< && d e , d &ed7d&d;;d &ded7 ef 7d&d;;d 7&, ; ?a e g = =# ?$,%c"a 7 7 7 7& $,!$ ; $,"$ $,!$ = $,:$ =# $,5c" e #,"" g #,$$ #
rclamp0524pq final datasheet rev 2.0 revision date june 22, 2015 www.semtech.com 9 of 10 semtech marking code %$+@6%6 %$+ bbcc tape and reel speci cation
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rclamp0524pq final datasheet 2.0 revision date june 22, 2015 10 of 10 semtech contact information semtech corporation 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111, fax: (805) 498-3804 www.semtech.com important notice information relating to this product and the application or design described herein is believed to be reliable, however such information is provided as a guide only and semtech assumes no liability for any errors in this document, or for the application or design described herein. semtech reserves the right to make changes to the product or this document at any time without notice. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. semtech warrants performance of its products to the speci cations applicable at the time of sale, and all sales are made in accordance with semtechs standard terms and conditions of sale. semtech products are not designed, intended, authorized or warranted to be suitable for use in life-support applications, devices or systems, or in nuclear applications in which the failure could be reasonably expected to result in personal injury, loss of life or severe property or environmental damage. inclusion of semtech products in such applications is understood to be undertaken solely at the customers own risk. should a customer purchase or use semtech products for any such unauthorized application, the customer shall indemnify and hold semtech and its o cers, employees, subsidiaries, a liates, and distributors harmless against all claims, costs damages and attorney fees which could arise. the semtech name and logo are registered trademarks of the semtech corporation. all other trademarks and trade names mentioned may be marks and names of semtech or their respective companies. semtech reserves the right to make changes to, or discontinue any products described in this documen t without further notice. semtech makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for an y particular purpose. all rights reserved. ? semtech 2015

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